1. Technical Field
The present disclosure relates to electrically erasable and programmable non-volatile memories (EEPROM). The present disclosure relates more particularly to a non-volatile memory, comprising memory cells each comprising a floating-gate transistor and an embedded vertical select transistor gate shared with a so-called “twin” adjacent memory cell.
2. Description of the Related Art
FIG. 1 is a wiring diagram of memory cells C11, C12 of the above-mentioned type, belonging to two adjacent pages Pi, Pi+1 of a memory array. The memory cells C11, C12 are read- and write-accessible through a bit line BL, a word line WL<i,i+1> and control gate lines CGL<i>, CGL<i+1>. Each memory cell comprises a floating-gate transistor FGT. The control gate CG of the transistor FGT of the cell C11 is connected to the control gate line CGL<i> through a contact C4. The control gate CG of the transistor FGT of the cell C12 is connected to the control gate line CGL<i+1> through a contact C4. The drain regions of the transistors FGT are connected to a bit line BL through contacts C1. Furthermore, each floating-gate transistor FGT has its source terminal coupled to a source line SL through a respective select transistor ST. The select transistors ST share a same select control gate SGC. The two memory cells C11, C12 are referred to as “twins” due to the fact that they share the same select control gate SGC and the same bit line BL. The common control gate SGC is a vertical gate embedded in a substrate accommodating the memory array, and is in contact with the source line SL formed by a region doped deep down in the substrate. The gate SGC is connected to a word line WL<i,i+1> common to the two memory cells through a contact C3. The channel regions CH1, CH2 of the transistors FGT, ST are at the electric potential of the well PW, as represented by dotted lines. Finally, the source line SL can be connected through a contact C5 to a main source line produced in a level of metal.
FIG. 2 is a schematic cross-section of two twin memory cells C11, C12, comprising a vertical select transistor gate SGC, common to the two memory cells. The memory cells C11, C12 are produced on a P-type conductivity substrate PW. The substrate is formed in a semiconductor wafer WF. The well PW is isolated from the rest of the wafer WF by an N-doped isolation layer n0 surrounding the entire well. Each memory cell C11, C12 comprises a floating-gate transistor FGT and a select transistor ST. Each floating-gate transistor FGT comprises a drain region n1, a source region n2, a floating gate FG, a state control gate CG, and a channel region CH1 extending beneath the floating gate FG between the drain n1 and source n2 regions. The vertical select gate SGC is embedded in the substrate PW and isolated from the latter by an insulating layer D3, for example made of oxide SiO2, forming the gate oxide of the select transistors ST. The region n2 extends along an upper edge of the embedded vertical gate SGC. The gate SGC reaches a source region n0 common to the select transistors ST, which thus forms a source line SL of the select transistors ST. Each select transistor ST thus comprises a drain region common to the source region n2 of the floating-gate transistor FGT of its cell, the common source region n0, and a channel region CH2 extending vertically along the gate SGC between the drain n2 and source n0 regions.
The regions n1, n2 are generally formed by N-doping of the substrate PW. The floating gates FG are generally made of level-1 polycrystalline silicon, or “poly1”, and are formed on a tunnel oxide layer D1 formed on the substrate PW. The state control gates CG are generally made of level-2 polycrystalline silicon, or “poly2”. Each state control gate CG is formed on one of the floating gates FG previously covered with an oxide layer D2. The gate SGC is formed in a trench filled with level-0 polycrystalline silicon, or “poly0”, isolated from the substrate by the oxide layer D3. Depending on the manufacturing method chosen, the conducting trench forming the gate SGC may not have any electrical discontinuity. It may then be used directly as word line WL.
The two memory cells C11, C12 are covered with a dielectric insulating material D0, which may also be oxide SiO2. The drain regions n1 of the floating-gate transistors FGT are coupled to a same bit line BL through a contact C1 passing through the insulating material D0.
FIGS. 3 and 4 represent the wafer WF in a cross-section and in a top view. FIGS. 3 and 4 show the layer n0 which delimits the well PW in the wafer WF. The layer n0 may be formed by two implantations of N-type dopants. A first implantation enables a horizontal layer of doped semiconductor to be formed that delimits the bottom of the well PW. A second implantation enables vertical walls of the well PW to be formed. FIG. 4 also shows the contacts C5 on the upper edge of the walls of the isolation layer n0. As the layer n0 is used as source line, many contacts C5 are preferably provided along the upper edge of the walls of the layer n0, as represented in the figure, so as to reduce its electrical resistance and foster the distribution of current lines in all directions. As indicated above, the contacts C5 enable the layer n0 to be coupled to a main source line SL made in a level of metal, or to control units for controlling the source line voltage.